1. Field of the Invention
This invention relates to reset circuits for single chip memory cells and, more specifically, to a reset circuit for CMOS memory cells capable of operation at very high speed and very low power.
2. Brief Description of the Prior Art
Reset circuits as presently known in the art for use in conjunction with CMOS memory cells are of relatively low operating speed, utilize a relatively large amount of chip real estate and dissipate a relatively large amount of power. CMOS memory cells of the prior art, as shown in FIG. 1, normally include six transistors, two of the transistors, Q1 and Q2, being n-channel pass transistors and being controlled via their gate electrodes by one of the word lines of the memory cell array. Such memory cells are also composed of two pairs of cross-coupled transistors, each pair including series connected n-channel pull down and p-channel pull up transistors. The equivalent circuit of the memory cells is a pair of inverters connected in parallel but operating in opposite directions. The pass transistors are coupled via their source to one of the bit line or bit line bar. These memory cells have data read thereinto to latch a particular logical state therein which can be read out later in known manner.
A problem arises in that, when the memory cells are to be reset, all of the word lines must be turned on and the bit lines are placed in a predetermined reset state. If, for example, all of the cells in a column store a logical "1" and these cells are all to be reset to a logical "0", during reset, the cells are actually driving the bit lines rather than vice versa. In order to remedy this problem in the prior art, it has been necessary that the reset transistors M1 and M2 be of very large size in order to supply a large amount of current and that these transistors be turned on for a substantial period of time in order to insure that the cells are in fact reset and that the driving power of the cells to be reset is neutralized and overpowered by the resetting current. It is readily apparent that the greater the number of cells in a column, the greater is the amount of current required to reset the memory array and, accordingly, the reset transistors must therefore be very large in order to over power the memory cells. These remedies, while providing the intended result, actually are a trade-off in that they increase the amount of chip real estate which must be used by the reset transistors and which also will create a very large transient current during reset. Also, the increased time used for reset slows down the speed of chip operation.
In addition, when a memory cell is accessed, the drain nodes of the p-channel and n-channel transistors, noted as A or B, for example, in FIG. 1, is at a voltage level Vcc - Vth (the threshold voltage drop through the pass transistor Q1 or Q2 or the threshold voltage thereof). Transistors Q1 and Q2 have their bulk tied to ground whereas their source nodes are not at the same potential, producing the body effect on said transistors Q1 and Q2. The absolute value of the threshold voltage of transistor Q2, being process dependent, may therefore by higher than that of transistor MP2 or MP1. Accordingly, transistor MP1 will be slightly turned on since node A drops below the threshold of the p-channel transistor MP1. For this reason, the cell will have a d-c current flow from Vcc through transistors MP2 and MN2 to ground. The same analysis is true for transistors Q1, MP2 and MN2. The above current flow will be small, however since such current flow can take place in many or all of the cells, the ultimate current can be high and dissipate a great deal of power.